Chain-code correlator

ABSTRACT

A chain-code correlator for determining the response of apparatus such as servomechanisms to command signals has a chaincode generator of m stages and clock-frequency fo connected through a first sampler to an output circuit connected to apparatus to be tested. The sampler provides samples of the code at a recurrence frequency fo/2m. An input from the apparatus under test is connected through a synchronized second sampler to a multiplier where it is multiplied by the chain code. The output of the multiplier is applied to an averaging memory of 2m-1 stages giving the correlation function for (2m-1) time delays at increments of 1/fo. Only m shift registers are required for (2m1) time delays.

United States Patent Wold 51 Mar. 7, 1972 CHAIN-CODE CORRELATOR PrimaryExaminer-Eugene G. Botz Assistant Examiner-R. Stephen Dildine, Jr.Inventor: Ivar Wold, Famboroush, HamPshlre, Attorney-William R. Sherman,Stewart F. Moore, Jerry M.

' gland Presson and Roylance, Abrams, Kruger, Berdo and Kaul [73]Assignee: The Solartron Electronic Group Limited,

Farnborough, Hampshire, England [57] ABS CT A chain-code correlator fordetermining the response of ap- [22] Filed May 1970 paratus such asservomechanisms to command signals has a 21 APPL 40 33 chain-codegenerator of m stages and clock-frequencyf, connected through a firstsampler to an output circuit connected to apparatus to be tested. Thesampler provides samples of the [30] Foreign Application Priority Datacode at a recurrence frequency f,,/2". An input from the apparatus undertest is connected through a synchronized May 28, 1969 Great Bl'ltall'l..27,045/69 Second Sampler to a multiplier where it is multiplied y thechain code. The output of the multiplier is applied to an [52] US. Cl...235/18l, 324/11 1, 324/158 SM averaging memory f L stages giving thecon-elation m [51] Int. Cl- ..H03k 5/18, 0011' 31/28 tion for (T -1)time delays at increments of l/f,, Only m Shift [58] Field of Search..235/181; 324/1 1 l, 158 SM registers are required for (2"1 timedelays.

[56] References Cited 5 Claims, 3 Drawing Fig!!!es W UNITED STATESPATENTS V 3,046,545 6/1962 Westerfield ..235/181 X 0UTPUT TIME EXPANDEDCHAIN (ODE OUTPUT m-smcr 0mm c005 am. p51, NETWORK P10! -32 SAMPLER [mmX T 35 AVERAGING nmom' i 4 @MPLE conmno I (LOEK n=2"'-/ 574655 a 29 x CI LfOo K 7 2 2757 I RESET 1 I2 I] g I 30 Patented March 7, 1972 2Sheets-Sheet I llllllllllullllll lll-llllllll'lllll llllllllllll'll'll'lllll l'llllll' lull-In CHAINCODECORRELATOR The present inventionrelates to a chain-code correlator. A knowledge of the response (ortransfer function) of various types of apparatus, such asservomechanisms, is often.

required by engineers when designing such apparatus or when testing theability of such apparatus to carry out prescribed functions.

There are several different ways in which the transfer function can bedetermined and one of these is to correlate the response to-randominputs with the random inputs. For this purpose various techniques havebeen proposed such as those byWiener in-Extrapolation Interpolation andSmoothing of Stationary Time Series" published by John Wiley & Sons1957.

Random test signals are applied to the system under test and theresponse of the system is'correlated with the test signals to derive thetransfer function.

Toeffect this in one proposal the random test signal and the output ofthe apparatus under test are multiplied at different time delays andaveraged. This technique, however, has demanded the use of a largenumber of shift registers and it is an object of the present inventionto provide a correlator in which the number of shift registers requiredcan be reduced, substantially with consequent simplification ofapparatus.

The invention makes use of a chain-code generator which is a knowndevice, such as the Solartron Pseudo Random Signal. Generator JMl86l,for generating a pseudorandom sequence of signals. The code generated byfeedback shift registers and repeats every (2'"1)f,, where m is thenumber of stages in the generator and f, is the clock frequency. Suchsignals are suitable for providing sufficiently random test signals forapplication to apparatus in testing its response.

According to the present invention there is provided a chain-codecorrelator comprising a chain-code generator of m stages andclock-frequency f, connected through a first sampler to an outputcircuit for connection to apparatus of which the impulse response is tobe tested, the sampler being arranged to provide samples of thegenerated chain-code at a recurrence frequency of f /2'", an inputcircuit for connection to the output of the apparatus to be testedconnected through a second sampler to a multiplier, the second samplerbeing arranged to operate in synchronism with the first sampler, meansfor applying the output of the chain-code generator also to themultiplier, and means for applying the output of the multiplier to anaveraging memory of 2"-l stages and arranged to provide an outputrepresentative of the correlation function of the outputs of the firstand second samplers for (2"-l time delays at increments of l/f,,. Thusby means of the invention a correlator can be provided in which only mshift registers are required for (2"'-l) time delays. For example, onlya 7-bit long register is required for 127 different time delays wherebya relatively simple correlator can be provided.

The invention will now be described, by way of example, with referenceto the accompanying drawings, in which:

FIG. 1 is a block diagram of one embodiment of the invention,

FIG. 2 is an explanatory diagram for use in conjunction with FIG. 1, and

FIG. 3 is a block diagram of an averaging memory for use in theembodiment of FIG. 1.

Referring to FIG. I, a chain-code correlator for use in determining theimpulse response of apparatus such as servo apparatus comprises achain-code generator 31 of m stages. The output of the chain-codegenerator 31 is applied through a sampler 32 to apparatus 33 of whichthe impulse response is to be determined. The effect of the sampler isto time-expand the chain-code.

The output of the apparatus 33 under test is applied to a second sampler34 arranged to operate in synchronism with the first sampler 32. Theoutput of the second sampler 34 and the output of the chain-codegenerator 31 are multiplied in a multiplier 35.

A clock pulsegenerator 12 of 'frequency f, is provided for driving thechain-code generator and: command pulses for operating the samplers 32andr34 are derived from the generator 12 by a frequency-divider 13 witha division ratio of 2".

The output of the multiplier 35. is applied to an averaging memory 28 of2"!--l stages, operating clock-pulses beingapplied thereto from theclock-pulse generator 12 and resetting pulses being applied atterminal30 from the divider 13.

At outputs V and V, of the averaging'memory 28 there appear signalssuitable for displaying-the impulse response of the apparatus 33-on acathode-ray tube. FIG. 2 shows thegeneral form of the response curve 36displayed on the cathode-rayv tube. a

The chain-code generators, the samplers, the multiplier and theaveraging memory are known devices but for completeness the averagingmemory which is less well. known will be described briefly.

A block diagram of the averaging-memory is shown in FIG. 3 and maybeasdescribedinthe P 'nceton Applied Research Corporation TechnicalBulletin T 162*. The input terminal 27; is connected through anamplifier A, and a resistor N!) to a rail 1. Between the rail J andearth is. an array of capacitors C C C each with a series connectedswitch 8,, S, S The switches are controlled by a sequential scanner S insuch a way that they are closed for a short period in turn by clockpulses applied at 29, only one switch being closed at any one time. Eachcycle or scan is made to repeat by a reset pulse applied at 30.

The rail J is connected to the input of an amplifier A which is arrangedto have a very high input impedance. Thus with any one of the switchesclosed, say switch 8,, the output from the amplifier A is the voltagestored on the capacitor C, which approaches. the value of the inputsignal at 27 in the interval when S is closed.

It will be appreciated therefore that in each scanning cycle thevoltages on the capacitors are modified to a new estimate of averagewhich appears at the same time at the output terminal V,, of theamplifier A The sequential scanner S is arranged to provide an output atV, proportional to memory position, i.e. with switch S closed the outputvoltage is V, where V is a constant voltage. Thus the output at V can bedisplayed on a cathode-ray tube using V for horizontal deflection and Vfor vertical deflection.

In FIG. 1 the averaging memory of FIG. 3 is provided with 2,,,l stagesand it will be appreciated that following the beginning of each scanningcycle the r'" product is always put into the r'" position in theaveraging memory. The output from the multiplier 35 (FIG. 1) for eachsample period will be the sample of the output y of the apparatus 33 forthe period multiplied by the successive outputs x x x etc. of thechaincode generator during the period, of which there are 2".

Thus the voltage on, say, C, in the averaging memory will approach thecorrelation between x(r) and y(z) at a delay of 'r,l=r/f., seconds. Anoscilloscope connected to display V against V 2 will show thecorrelation function (as shown for example in FIG. 2) for 2" differenttime delays at increments of l/f,,.

In the known averaging memory shown in FIG. 3 the resistor R(t) is fixedin value. We have found that true timeaveraging can be obtained byarranging that R(t) is increased before or after each scanning cyclesuch that the averaging RC time constant is approximately equal to thetime which has elapsed since the start of the measurement. This can bearranged by means of a suitable network or array of resistors which areswitched through appropriate switches controlled by a counter which isincremented after each scan.

What I claim is:

1. A chain-code correlator, comprising a chain-code generator of mstages, a source of clock pulses of frequency f,

. connected to said chain-code generator, a first sampler connectedbetween the output of said chain-code generator and an output terminalfor connection to apparatus to be tested,

means coupling said source to said first sampler to drive said firstsampler at a recurrence frequency of f /2'" and time-expand the codegenerated by said chain-code generator for application to said outputterminal, an input terminal for connection to the output of theapparatus to be tested, a second sampler in synchronism with said firstsampler at said input terminal, means for providing a signal to drivesaid second sampler in synchronism with said first sampler at saidrecurrence frequency f /2", a multiplier, means connecting the output ofsaid chain-code generator to one input of said multiplier, meansconnecting the output of said second sampler to another input of saidmultiplier, an averaging memory of 2"l stages, means for providing adriving signal to said memory at said clock frequency f,,, means forproviding a signal to reset said averaging memory at said frequency f/2', and means to apply the output of said multiplier to the input ofsaid averaging memory. 7

2. A chain-code correlator according to claim 1, wherein said multiplieris a binary multiplier.

3. A chain-code correlator according to claim I, wherein said meanscoupling said source to said first sampler comprises a frequency dividerof division ratio 1/2" connected between said source and said firstsampler.

4. A chain-code correlator according to claim 3, wherein said means forproviding a signal to drive said second sampler includes a conductor forproviding thereto the output of said frequency divider.

5. A chain-code correlator according to claim 4, wherein said means forproviding a signal to reset said averaging memory includes a conductorconnected to supply the output of said frequency divider.

nun-v

1. A chain-code correlator, comprising a chain-code generator of mstages, a source of clock pulses of frequency fo connected to saidchain-code generator, a first sampler connected between the output ofsaid chain-code generator and an output terminal for connection toapparatus to be tested, means coupling said source to said first samplerto drive said first sampler at a recurrence frequency of fo/2m andtime-expand the code generated by said chain-code generator forapplication to said output terminal, an input terminal for connection tothe output of the apparatus to be tested, a second sampler insynchronism with said first sampler at said input terminal, means forproviding a signal to drive said second sampler in synchronism with saidfirst sampler at said recurrence frequency fo/2m, a multiplier, meansconnecting the output of said chain-code generator to one input of saidmultiplier, means connecting the output of said second sampler toanother input of said multiplier, an averaging memory of 2m-1 stages,means for providing a driving signal to said memory at said clockfrequency fo, means for providing a signal to reset said averagingmemory at said frequency fo/2m, and means to apply the output of saidmultiplier to the input of said averaging memory.
 2. A chain-codecorrelator according to claim 1, wherein said multiplier is a binarymultiplier.
 2. A chain-code correlator according to claim 1, whereinsaid multiplier is a binary multiplier.
 3. A chain-code correlatoraccording to claim 1, wherein said means coupling said source to saidfirst sampler comprises a frequency divider of division ratio 1/2mconnected between said source and said first sampler.
 3. A chain-codecorrelator according to claim 1, wherein said means coupling said sourceto said first sampler comprises a frequency divider of division ratio1/2m connected between said source and said first sampler.
 4. Achain-code correlator according to claim 3, wherein said means forproviding a signal to drive said second sampler includes a conductor forproviding thereto the output of said frequency divider.
 5. A chain-codecorrelator according to claim 4, wherein said means for providing asignal to reset said averaging memory includes a conductor connected tosupply the output of said frequency divider.